(a) Field of the Invention
The present invention relates to integrated circuit technology in general and more particularly relates to the use of FET devices to form substrate voltage generators on an integrated circuit chip.
(b) Prior Art
The fabrication of electrical devices from integrated circuit technology is well known in the prior art, and includes functional units such as Random Access Memory (RAM), Read Only Memory (ROM), gate arrays, programmable logic arrays (PLA), etc. These devices generally consist of a plurality of electrical components and/or functional units on a substrate. The substrate with its electrical components and/or units is often referred to as a chip.
One of the important characteristics of a chip is that a relatively large number of electrical circuits are placed on a relatively small surface area. In an attempt to economize on the system power supplies and or chip I/O pins, only a single voltage source is usually made available to the chip. Usually, the voltage source is positive and is stubbed onto a designated pin on the chip. For most applications, both a positive and a negative voltage level is needed on the chip. The negative voltage level is used to bias the substrate of the chip.
In order to generate the negative supply voltage, the prior art uses an on-chip voltage generator. U.S. Pat. No. 4,208,595 is an example of a prior-art on-chip voltage generator. The voltage generator consists of an FET circuit which applies the principle of voltage doubling to a first capacitor to achieve a predetermined voltage magnitude across a second capacitor. The voltage on the second capacitor is inverted and is coupled into the substrate of the chip.
An article entitled, "Substrate Voltage Generator Circuit," published in the IBM Technical Disclosure Bulletin, Vol. 21, No. 2, July 1978 (pages 727-728), describes an FET circuit for generating a negative voltage on a chip. The circuit includes two capacitors, a diode, two switching devices and a clock signal. The capacitors, diode and switching devices are connected so that when the clock is in its high state, a current path leads from ground through the switching devices, the capacitors and the diode into the substrate. This path provides the negative voltage to the substrate.
One of the problems which plagues the prior art on-chip generators is that the generated voltage is susceptible to wide variation having an adverse effect on the performance of the chip. The prior art adopts several techniques to control the generated voltage.
One of the prior-art techniques is the so-called threshold-voltage compensation technique. In this technique, circuitry is provided to maintain tight control over the threshold voltage of a reference FET. U.S. Pat. No. 4,049,944 is an example of this prior-art technique. In the patent a pair of FETs generate a reference voltage which is supplied to a sensing circuit consisting of FETs. One of the FETs of the sensing circuit is designated the control FET. The referenced voltage is applied to the base of the controlled FET. The sensing circuit senses the threshold voltage across the controlled FET and generates a control voltage in response to the threshold voltage. A regulating circuit utilizes the control voltage to vary a current through a resistor. The current is used to bias the substrate voltage, thereby compensating for variations in the threshold voltage.
Another example of prior-art threshold-voltage compensation technique is given in an article entitled, "FET N-Channel Threshold Voltage-Control Circuit", published in the IBM Technical Disclosure Bulletin, Vol. 17, No. 1, June 1974 (p. 140). In the article a pair of FET devices establishes a reference voltage. The reference voltage controls the threshold voltage of another FET device. When the threshold voltage is below the reference level, the substrate bias is made more negative.
In yet another prior-art technique, the substrate voltage of the chip is regulated. An article entitled, "Sentry Circuit for Substrate Voltage Control," published in Vol. 15, No. 2, July 1972 (pp. 478-479), is an example of this technique. A multivibrator circuit generates a square wave. A bias voltage control circuit rectifies the square wave and supplies a negative voltage to the substrate. A pair of enhancement FETs is connected between the supply voltage and the substrate. The pair of enhancement FETs form a voltage divider whose output voltage is used to regulate the output of the bias voltage control circuit.
In still another technique the substrate voltage generator is regulated by a capacitive voltage divider connected between substrate voltage and ground. This technique is described in an article entitled, "Feedback Substrate Bias Generator," published in the IBM Technical Disclosure Bulletin, Vol. 23, No. 5, October 1944 (pp. 1930-1931).
For overall power and performance control, compensation theoretically would be preferred over regulation. However, compensation requires a large overall range of substrate voltages, especially with state-of-the-art FETs having a low variation in threshold voltage with changing substrate voltage. Generation of a sufficiently wide range of substrate voltages taxes the current capability of feasible generator circuits, and leads to circuit problems such as device breakdown at high voltages and leakage at low voltages. Regulation provides substrate-voltage control with a much narrower range of generated voltages.
In the prior art, the regulator voltage divider was connected between the supply voltage and the substrate. Supply-voltage variations were therefore propagated into the reference voltage which controls the substrate generator. In another configuration, capacitive voltage dividers are used, but these block D.C. current from entering the substrate. The flow of D.C. current into the substrate minimizes negative voltage drift in the substrate and forces the substrate to operate around its quiescent voltage level.